Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change random access memory (PCRAM), and/or flash memory, among others.
Flash memory devices can be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and/or low power consumption. Uses for flash memory include memory for solid state drives (SSDs), automotive applications, aeronautic applications, surveillance applications, personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and/or movie players, among other electronic devices.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to, and in some cases from, an access line, which is commonly referred to in the art as a “word line”. However, each memory cell is not directly coupled to a sense line (which is commonly referred to as a “data line” or a “bit line” in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a sense line, where the memory cells commonly coupled to a particular sense line are commonly referred to as a “column” or a “string” in the art.
Memory cells in a NAND array architecture can be programmed to a targeted, e.g., desired, program state. For example, electric charge can be placed on or removed from a charge storage structure, e.g., a floating gate or charge trap, of a memory cell to put the memory cell into one of a number of program states. For example, a single level cell (SLC) can be programmed to one of two program states, e.g., one bit, so as to represent a binary data value, e.g., “1” or “0”, stored by the memory cell.
In a two-dimensional (2D) array of memory cells, some data storage errors may be managed by applicable error control techniques, e.g., such as redundant array of independent NAND (RAIN). However, such error control techniques may not be suitable for error control in, for instance, a 3D NAND architecture in which it is possible to have data storage errors in either tiers or pillars of memory cells.